1. Field of the Invention
The present invention relates generally to methods for fabricating semiconductor devices, and more particularly, to a technique for isolating active device regions in silicon-on-insulator devices.
2. Discussion of the Prior Art
Silicon-on-insulator ("SOI") is a VLSI semiconductor fabrication technique that provides for the isolation of circuit components, e.g., transistors, from each other. As is well known, this technique is advantageous in terms of enabling production of ICs having increased circuit density, speed and power improvement, immunity from latch-up and improved radiation hardness. Although not specifically drawn to SOI manufacturing techniques, issued U.S. Pat. No. 5,637,513 to Sugiyama, U.S. Pat. No. 5,258,318 to Buti, U.S. Pat. No. 5,650,354 to Himi et al., and, the references cited therein, explain how an SOI semiconductor device may be fabricated. Typically, in SOI, a layer of oxide, usually on the order of 3000 .ANG., is formed beneath all active device regions.
To isolate active device regions in SOI formed devices, a methodology commonly known as Shallow Trench Isolation ("STI") is implemented. For bulk devices, STI serves several purposes: 1) it electrically isolates devices, and 2) it provides low capacitance when polysilicon conductors "PC" or metallization "MC" runs over isolation between devices. FIG. 1(a) illustrates a photomicrograph depiction of a portion of a semiconductor wafer having formed silicon diffusion areas 20a-20d, localized MC interconnects 14 and PC gates 15 electrically interconnecting devices, e.g., in different diffusion regions 20a and 20b, and contacted over isolation.
FIG. 1(b) illustrates the cross-sectional view of the semiconductor region 10 taken along a portion of line A--A of FIG. 1(a). As shown in FIG. 1(b), PC conductors 15 and local MC interconnects 14 are shown formed within a diffusion region 20. However, it is the case that significantly wide areas of the device, particularly the region 10 formed between active diffusion regions 20a,b, must be formed of STI 12. This necessarily results when polyconductors 15 electrically connect components in two separate diffusion regions. These wide regions of STI, such as shown in FIG. 1(b), may be greater than 5.0 .mu.m wide.
In the known STI semiconductor fabrication techniques, first, a silicon on insulator structure is provided having a conducting layer superjacent the insulator of the SOI. Then, using well known etch techniques, a tapered sidewall trench is formed down to the insulator. Trench widths may range from about 0.3 .mu.m or greater. Typical techniques may include anisotropic etch such as described in U.S. Pat. No. 5,561,073. These trenches may be patterned using a simple nitride (on top of a thin pad oxide) isolation mask, with implementation of either i-line or deep ultraviolet lithography. Third, a SiO.sub.2 layer is formed conformally with the sidewalls of the trench of the first and second conductive regions. Fourth, the trench is refilled w/SiO.sub.2, preferably by undoped SiO.sub.2 such as "TEOS". Oxide coating applied conformally causes build-up or bumps in the area of the conductive region and extra planarization steps are needed to remove this build-up. Thus, after the TEOS deposition, a further etch step is usually required to remove the excess oxide, and finally, a CMP polish is performed to remove all remaining oxide down to the nitride. These steps usually are time-consuming and fairly complicate the otherwise simple, STI formation techniques.
It is readily surmised that the STI trench fabrication techniques as described above is expensive largely due to the extra steps required to achieve device planarization.
Thus, it would be highly desirable to provide an STI etching technique for use with SOI that is simple and cost-effective and that promotes the formation of STI without the time consuming etch-back and/or planarization steps.
Additionally, it would be highly desirable to provide an STI etching technique that promotes the fabrication of trenches using isolation images of minimum or near minimum size.